Assume that the $5-$stage pipelined processor supports precise exceptions. The processor also supports all kinds of data forwarding $($including the internal forwarding in the register file$)$ and hazard detection. Consider the following RISC$-$V assembly code.Let us assume that page fault is detected in the MEM stage and undefined instruction is detected in the ID stage. Draw a pipeline diagram as shown below. You should identify which exception handler is called and exhibit the first instruction of an exception handler such as PFI$0$ and UIIO in the diagram. Youcan use any unknown instructions such as INST if needed. Represent a flush $($a bubble$)"---".$ Show when exceptions are detected also by circling the corresponding pipeline stage. $[12]$

$\backslash$table$[[,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15],[$add $1,$IF$,$ID$,,,,,,,,,,,,,],[$addi $3,,,,,,,,,,,,,,,],[$lw $4,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,],[,,,,,,,,,,,,,,,]]$