Assume that the following code segment is run on a MIPS processor with hazard detection and...

   

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Assume that the following code segment is run on a MIPS processor with hazard detection and forwarding, in order, 5 stages pipeline (F (instruction fetch), D (instruction decode), E (execute), M (memory access, W (write-back)), static not taken branch prediction (branches are always predicted as not taken), etc.. Below is the code segment that is running on the processor. #code segment 10: 11: L1: 12: 13: 14: 15: L2: 16: 17: 18: 19: beq $R1, $RO, L2 lw $R5, 100($R4) # M[$R4+100] -> R5 sw $R2, 100($R1) # $R2 -> M[$R1 + 100] shl $R2, $R2, 1 beq $RO, $RO, L3 lw $R2, 100($R1) # M[$R1+100] -> $R2 addi $R2, $R2, 100 lw $R3, 100($R10 #M[$R1+100] -> R3 addi $R3, $R3, 1 beq $RO, $RO, STR L3: END a) How many cycles does this program take? Assume all data and instructions are already in the cache, and that all register values are initially O. The branches are always going to be evaluated as not taken. Note: END is an assembly directive, not an instruction. Activa b) An optimizing compiler is used to re-order the code for faster execution. Given that the branches are always going to be "not taken", and the compiler can eliminate them, how would the new code look like? How many cycles would the code take? Assume that the following code segment is run on a MIPS processor with hazard detection and forwarding, in order, 5 stages pipeline (F (instruction fetch), D (instruction decode), E (execute), M (memory access, W (write-back)), static not taken branch prediction (branches are always predicted as not taken), etc.. Below is the code segment that is running on the processor. #code segment 10: 11: L1: 12: 13: 14: 15: L2: 16: 17: 18: 19: beq $R1, $RO, L2 lw $R5, 100($R4) # M[$R4+100] -> R5 sw $R2, 100($R1) # $R2 -> M[$R1 + 100] shl $R2, $R2, 1 beq $RO, $RO, L3 lw $R2, 100($R1) # M[$R1+100] -> $R2 addi $R2, $R2, 100 lw $R3, 100($R10 #M[$R1+100] -> R3 addi $R3, $R3, 1 beq $RO, $RO, STR L3: END a) How many cycles does this program take? Assume all data and instructions are already in the cache, and that all register values are initially O. The branches are always going to be evaluated as not taken. Note: END is an assembly directive, not an instruction. Activa b) An optimizing compiler is used to re-order the code for faster execution. Given that the branches are always going to be "not taken", and the compiler can eliminate them, how would the new code look like? How many cycles would the code take?

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a To calculate the number of cycles the original code segment takes on a MIPS processor with ... View the full answer