Assume that you are given a dual-issue pipeline for RISC-V ISA. You can schedule ALU or...

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Assume that you are given a dual-issue pipeline for RISC-V ISA. You can schedule ALU or branch instruction in the first issue slot, and load/store instruction in the second issue slot of the issue package. You are given the following sequence of instructions. Loop: lw add SW addi bne x7, 0(x10) x7, x7, x11 x7, 0(x10) x10, x10, 0x4 x10, x12, Loop #read from memory #update value #store it back to memory #update the address #Loop until the address is not equal to the content of x12 a) [10 points] Assume that the loop index for the given loop above is divisible by 3. Unroll the given loop 3 times. Use register renaming as necessary to avoid any name dependencies. Package 1 Package 2 Package 3 Package 4 Package 5 Package 6 b) [10 points] How would the unrolled loop in (a) be scheduled on the given static dual-issue pipeline? You may use the following template to show the schedule. 1st Slot (ALU or branch) 2nd Slot (load or store) c) [5 points] Calculate and report the IPC of the system after the loop unrolling, separately. How much speedup achieved after loop unrolling? Assume that you are given a dual-issue pipeline for RISC-V ISA. You can schedule ALU or branch instruction in the first issue slot, and load/store instruction in the second issue slot of the issue package. You are given the following sequence of instructions. Loop: lw add SW addi bne x7, 0(x10) x7, x7, x11 x7, 0(x10) x10, x10, 0x4 x10, x12, Loop #read from memory #update value #store it back to memory #update the address #Loop until the address is not equal to the content of x12 a) [10 points] Assume that the loop index for the given loop above is divisible by 3. Unroll the given loop 3 times. Use register renaming as necessary to avoid any name dependencies. Package 1 Package 2 Package 3 Package 4 Package 5 Package 6 b) [10 points] How would the unrolled loop in (a) be scheduled on the given static dual-issue pipeline? You may use the following template to show the schedule. 1st Slot (ALU or branch) 2nd Slot (load or store) c) [5 points] Calculate and report the IPC of the system after the loop unrolling, separately. How much speedup achieved after loop unrolling?

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The question presents a code snippet that includes a loop and the task involves optimizing this loop for a dualissue pipeline in a RISCV instruction set architecture ISA processor ensuring that both i... View the full answer