Question: Assume the following information about a 2-level memory hierarchy system. Memory is byte addressable. Memory capacity is 4 GB (G=2^30). Cache capacity is 64 KB

Assume the following information about a 2-level memory hierarchy system.

Memory is byte addressable.

Memory capacity is 4 GB (G=2^30).

Cache capacity is 64 KB (K=2^10).

Block offset size is 8 bits.

Assuming that the CPU has generated the physical address X = (2293936063)10, answer the following questions.

a. If direct mapped is used, where will the block containing address X reside in cache? In other words, what is the cache address for the block containing address X?

b. If 2-way set associative is used, how many blocks are in the cache?

c. What is the memory physical address size? In other words, how many bits are in each physical address?

d. If direct mapped is used, how many segments are in the memory?

e. If direct mapped is used, what is the size of each segment in bytes?

f. If 2-way set associative is used, what is the size of each segment in bytes?

g. What is the block offset value (not size) for this physical address (i.e. X)? h. If direct mapped is used, what is the index size (not value)?

i. If 2-way set associative is used, what is the index size (not value)?

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