Assume the following The memory is byte addressable .Memory accesses are to 1-byte words (not to 4-byte words) Addresses are 13 bits wide The cache is two-way set associative (E2), with a 4-byte block size (B- 4) and eight sets (S 8) The contents of the cache are as follows, with all numbers given in hexadecimal notation 2-way set associative cache Line 0 Line 1 Set index Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 Tag Valid Byte 0 Byte 1 Byte 2 Byte 3 09 1 8630 3F 10 000 45 1 604F EO 23 38 100 BC OB 37 EB0 06 0 - C7 1 0678 07 C5 05 40 67 C2 3B 0B 0. 32 1 1208 7B AD 46 0 - DE 1 12CO 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following CO. The cache block offset CI. The cache set index CT. The cache tag