Assume the following The memory is byte addressable .Memory accesses are to 1-byte words (not to 4-byte words). . Addresses are 13 bits wide .The cache is two-way set associative (E 2), with a 4-byte block size (B4) and eight sets (S- 8). The contents of the cache are as follows, with all numbers given in hexadecimal notation 2-way set associative cache Line 0 ne Set index Tag Valid Byte Byte Byte Byte Byte Byte 0123Tag Valid yte 0 1 23 09 1 86 30 3F 10 00 0 - 45 1 60 4F E0 23 38 1 00BC 0B 37 OB 0 - 3 06 0 32 1 12 08 7B AD 4 C7 1 06 78 07 C5 05 1 4067 C2 3B 46 0 DE 1 12 CO 88 37 The following figure shows the format of an address (1 bit per box). Indicate (by labeling the diagram) the fields that would be used to determine the following CO. The cache block offset Cl. The cache set index CT. The cache tag