Assume you are designing a small MIPS processor that is word addressable. You want to in a small L$1$

cache that has $16$ rows. Each row contains exactly four words, and each memory address bits long.

Assume that the following memory sequence occurs:

$0$x$0$F$20,0$x$0074,0$x$0020,0$x$0078,0$x$0$F$24,0$xFOAC, $0$x$0$F$2$C$,0$x$0078$

a$)$ Write out the memory sequence in bits, and identify which bits are part of the byte offset, the index,

and the tag.

b$)$ Next to where you wrote out the memory addresses, indicate whether they would result i or a miss

given the sequence and cache.

c$)$ What is the hit rate of the cache? What is the miss rate of the cache?

d$)$ What is the total number of bits that would be required to create the cache including all overhead?