Assuming a CPU with a hardware-managed TLB (e.g., x86), clearly describe the events occurring between when the CPU executes a faulting load/store instruction and when this instruction is eventually able to execute successfully. Describe clearly the role played by hard- ware (MMU, TLB, cache/main memory controllers) if any as well as the OS. Also clearly identify all data structure manipulations (TLB and page table entries, free frame list, swap layout information) involved. Repeat the above for a CPU with a software-managed TLB (e.g., MIPS).Use timelines or diagrams similar to those in lectures (with additional text if needed) to explain your answer.