Assuming that each SRAM listed in the table below has 8 output lines: SRAM Size in bytes Rows Columns 8 512 8192 131072 8G Column Mux size a) If it is arranged optimally, how many rows and columns are in the organization? b) What is the size of the column multiplexer? c) Draw the logic gate-level schematic for an 8-bit active-low binary decoder that takes inputs SS1So and produces outputs [do: dz], where do is selected when SS1S0 = 000.