B$3($a$)$ The data of different logic families are shown in Table B$3$a$.$ Determine:

$($i$)$ high level noise margin $V_{NH}$ when a $74$ TTL drives a $74$LSTTL;

$(4$ marks$)$

$($ii$)$ low level noise margin $V_{NL}$ when a $74$ TTL drives a $74$LSTTL$.$

$(4$ marks$)$

$\backslash$table$[[\backslash$table$[[$Parameters$],[($volt$.)]],74$HCMOS,$74$TTL$,74$LSTTL$],[V_{IH(min.)},2\mathrm{.}2,2\mathrm{.}7,2\mathrm{.}2],[V_{IL(max.)},1\mathrm{.}0,1\mathrm{.}2,1\mathrm{.}0],[V_{OH(min.)},3\mathrm{.}0,3\mathrm{.}5,2\mathrm{.}8],[V_{OL(max.)},0\mathrm{.}5,0\mathrm{.}3,0\mathrm{.}5]]$

Table B$3$a

$($b$)$ Determine the overall noise margin when a $74$TTL drives a $74$LSTTL$.$

$(4$ marks$)$