(b) A direct mapped cache with a 4 lines and an 8-byte line size is shown below. Suppose the cache is accessed by a sequence of load word instructions with the following addresses (in hexadecimal): 0x04, 0x05, 0x68, 0xC8, 0x68, 0xDD, 0x45, 0x04, 0xC8 Classify each of the accesses as a cache hit (H), a cache miss (M), and a cache miss with replacement (R). (c) Cache misses can be classified as follows: Compulsory: On the first access to a block; the block must be brought into the cache; also called cold start misses, or first reference misses. Reduce compulsory misses by having a longer cache line, which brings in locations before we ask for them. Conflict: In the case of set associative or direct mapped block placement strategies, conflict misses occur when several blocks are mapped to the same set or block frame; also called collision misses or interference misses. Miss to an address because that address Increasing the associativity or improving the replacement policy would remove the miss. Capacity: Occur because blocks are being discarded from cache because cache cannot contain all blocks needed for program execution (program working set is much larger than cache capacity). The only way to remove the miss is to increase the cache capacity Classify each of the misses from the previous problem as compulsory, conflict, or capacity misses