2. Consider the following assembly code. Assume that initial values of all registers and memory are...

Transcribed Image Text:

2. Consider the following assembly code. Assume that initial values of all registers and memory are zero. Assume a five stage pipelined architecture with the following stages: F= fetch, D = decode, X = execute, M = memory access, W = write back. Also assume that registers are written in the first half of the cycle and read in the second half of the cycle and that branches are resolved during decode. There are two types of simplified branch instructions: 1) “beqz rl" means branch if rl is zero, and 2) "bnez rl" means branch if r1 is not zero. Answer parts a and b on the following two pages. In part a, we assume a processor with forwarding. In part b, we assume a processor without forwarding. a) Assume there is forwarding. Fill in the pipeline timing diagram at the bottom showing the execution of the code given below. The first instruction is filled in for you. Show only the first ten instructions executed. [List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.] Fill in write back cycle of each instruction (continued on next page): Instr. No. Instruction Write back cycle rl,r0,5 r2,100 (r1) r2, L2 (1) addi 4 (2) lw (3) (4) beqz sub r7,r2,r3 r5,13 (r2) r2,r5, r2 r2,L3 (5) L1: lw (6) and (7) bnez r6,r3,r2 r6,L1 r2,r6, rl (8) sub (9) L2: bnez (10) L3: or instruction 1 3 4 5 6. 7 8 10 11 12 13 14 15 16 | 17 18 19 (1) F D M W instruction 20 21 22 |23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 b) Assume there is NO forwarding. Fill in the pipeline timing diagram at the bottom showing the execution of the code given below. The first instruction is filled in for you. Show only the first ten instructions executed. [List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.] Fill in write back cycle of each instruction (continued on next page): Instr. No. Instruction Write back cycle addi rl,r0,5 r2,100 (r1) (1) 4 (2) lw r2, L2 r7,r2, r3 r5,13 (r2) r2,r5,r2 r2,L3 (3) beqz (4) sub (5) L1: lw (6) and (7) bnez r6,r3,r2 r6,L1 (8) sub L2: (9) (10) bnez L3: or r2,r6,rl instruction 1 2 4 7 8 9 10 11 12 13 14 15 16 17 18 19 (1) F D X M W instruction 20 |21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 6 2. Consider the following assembly code. Assume that initial values of all registers and memory are zero. Assume a five stage pipelined architecture with the following stages: F= fetch, D = decode, X = execute, M = memory access, W = write back. Also assume that registers are written in the first half of the cycle and read in the second half of the cycle and that branches are resolved during decode. There are two types of simplified branch instructions: 1) “beqz rl" means branch if rl is zero, and 2) "bnez rl" means branch if r1 is not zero. Answer parts a and b on the following two pages. In part a, we assume a processor with forwarding. In part b, we assume a processor without forwarding. a) Assume there is forwarding. Fill in the pipeline timing diagram at the bottom showing the execution of the code given below. The first instruction is filled in for you. Show only the first ten instructions executed. [List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.] Fill in write back cycle of each instruction (continued on next page): Instr. No. Instruction Write back cycle rl,r0,5 r2,100 (r1) r2, L2 (1) addi 4 (2) lw (3) (4) beqz sub r7,r2,r3 r5,13 (r2) r2,r5, r2 r2,L3 (5) L1: lw (6) and (7) bnez r6,r3,r2 r6,L1 r2,r6, rl (8) sub (9) L2: bnez (10) L3: or instruction 1 3 4 5 6. 7 8 10 11 12 13 14 15 16 | 17 18 19 (1) F D M W instruction 20 21 22 |23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 b) Assume there is NO forwarding. Fill in the pipeline timing diagram at the bottom showing the execution of the code given below. The first instruction is filled in for you. Show only the first ten instructions executed. [List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.] Fill in write back cycle of each instruction (continued on next page): Instr. No. Instruction Write back cycle addi rl,r0,5 r2,100 (r1) (1) 4 (2) lw r2, L2 r7,r2, r3 r5,13 (r2) r2,r5,r2 r2,L3 (3) beqz (4) sub (5) L1: lw (6) and (7) bnez r6,r3,r2 r6,L1 (8) sub L2: (9) (10) bnez L3: or r2,r6,rl instruction 1 2 4 7 8 9 10 11 12 13 14 15 16 17 18 19 (1) F D X M W instruction 20 |21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 6

Answer rating: 100% (QA)

The generated pipleine diagram is as follows instruction 0 2 3 4 56 78 9 ... View the full answer