(b) Compare a 3-stage pipeline computer with a 5-stage one. The 3-stage pipeline is better since it takes 3 cycles to complete a job while its counterpart takes 5 cycles. [] True [] False (c) Page fault means that the data to be referenced is not in the cache. [] True [] False (d) Suppose a cache contains m blocks in total. It includes m sets if it is n-way set associative [] True [] False (e) After translating the virtual address to physical address, the physical address includes more bits than the virtual address in order to represent page numbers. [] True [] False Consider the implementation of a "store" instruction on the non-pipeline datapath given in 1(a). (a) Highlight the active datapath/blocks. (b) Set the control signals properly to implement "store": ALUSrc = ______ RegWrite = ______ MemtoReg = ______ Reg2Loc = ______ MemRead = ______ MemWrite = ______