Question: [ b ] Consider a 4 - stage instruction pipeline and four instructions need to be [ b ] Consider an array of 1 0

[b] Consider a 4-stage instruction pipeline and four instructions need to be[b] Consider an array of 100 elements, where each element of an array
occupies 4 words in the memory. The size of the entire cache is 32 words.
The cache is further divided into 8-words per block/line of cache. Consider
the following statement:
for (i=0;i10,i++)
q for (j=0;j10;j++)
,A[i][j]=A[i][j]+10;
Find the hit ratio of the above code if the elements of the 2-D array are stored
in row-major order. How does the hit ratio change if the elements are stored
in column-major order?
executed on the pipelined processor. The instructions consume different
number of clock cycles at different stages as shown below:
The following code has to be executed on the pipelined processor:
I1 instruction is first executed followed by 12,13 and 14, and the process repeats 100
limes. After how many clock cycles the output of the instruction 12 for j=2 will be
available?
[ b ] Consider a 4 - stage instruction pipeline

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