b$)$ Design and draw the typical cell $A_i$ of register $A$ as specified below using formal design method or separate design

method with a D FF$.$ Indicate the method that you use. Show all steps of the design. Assume that $P_1*P_2=0$ is always

satisfied. If $P_1+P_2=0,$AlarrA.

$P_1$:AlarrA$+B,($logical OR$)$

$P_2$:AlarrA.$B,($logical AND$)$

In your drawing, clearly show the typical register cell $A_i$ with its $DFF,$ the required Boolean expressions $($along with $A_i,$

$B_i),$ and the clock. Do not draw the gates for these Boolean expressions; write down the expressions where needed in the

drawing.