b)	You are asked to design a 32 bit adder circuit for a microprocessor with the following design constraint. The result (sum) should be stable within one clock cycle when the clock frequency is 50 MHz and the silicon technology used has a propagation delay for logic gates of 1 ns.
	i)	Describe the design of a serial adder using one full adder circuit and various shift registers (a simple circuit diagram may be used). Why does this design fail to satisfy the design constraint given above?
	ii)	Describe the design of a ripple carry adder (a circuit diagram for 4 bits may be included). Why does this design fail to satisfy the design constraint given above?
	iii)	Describe the design of a carry look ahead adder. Give the Boolean equation for Cout in terms of propagate, P, generate, G and Cin. What are the criteria for setting the P and G logic signals for an n bit adder block? Does this design satisfy the design constraint given above?
	iv)	Find Boolean equations for the P and G logic signals for a 3 bit adder block with inputs (A2A1A0) and (B2B1B0) using map entered variables.