Based on the table provided I need to find out the total latency for these three instructions for pipelined processor and non-pipelined processor. Thanks! Will give upvote :)

c) Find the total latency for each of the R-type, lw, sw, and beq instructions for both nonpipelined and pipelined processor. The total latency comprises of the total of all active phases. Ignore the PC write time. [15 Points) Question 1. Assume that the MIPS stages have these latencies (in ps): Instruction Register Execute Data Register Memory Read Memory Write 200 100 100 250 150