beg 1. (6 points - Correctness) Data and Control Hazards. Luigi wants to run the following program on the 5-stage pipelined MIPS processor (Show your work to get full credit). lw $ti, 4($a0) lw $tz, 8 ($tl) and $t3, $t2, Sal $a3, $t3, target addi $t3, $t2, 5 SW $t3, -8 ($t1) target: lw $t2, 4($a0) add $t5, $t4, $t2 (a) Draw arrows to show all data dependencies between instructions. (b) Assuming forwarding wherever possible, branches are resolved in Decode, and branches are always predicted not-taken, fill the following table showing the execution stages, data forwarding, stalls, and flushed instructions. Fill the table for the case when the branch will be taken (There is no branch delay slot the architecture DOES NOT assume the instruction after the branch is always executed.). 1 2 3 4 5 6 7 89 10 11 12 | 13 | 1 14 15 16 17 lw $t1, 4($a0) lw $t2, 8($t1) beg 1. (6 points - Correctness) Data and Control Hazards. Luigi wants to run the following program on the 5-stage pipelined MIPS processor (Show your work to get full credit). lw $ti, 4($a0) lw $tz, 8 ($tl) and $t3, $t2, Sal $a3, $t3, target addi $t3, $t2, 5 SW $t3, -8 ($t1) target: lw $t2, 4($a0) add $t5, $t4, $t2 (a) Draw arrows to show all data dependencies between instructions. (b) Assuming forwarding wherever possible, branches are resolved in Decode, and branches are always predicted not-taken, fill the following table showing the execution stages, data forwarding, stalls, and flushed instructions. Fill the table for the case when the branch will be taken (There is no branch delay slot the architecture DOES NOT assume the instruction after the branch is always executed.). 1 2 3 4 5 6 7 89 10 11 12 | 13 | 1 14 15 16 17 lw $t1, 4($a0) lw $t2, 8($t1)