Behavioral modeling is used to describe complex circuits. It is primarily used to model sequential circulte, but can also be used to model pure combinatorial drcuits. The mechanisms (statements) for modeling the behavior of a design are: initial Statements always Statements A module may contain an arbitrary number of initial or always statements and may contain one or more procedural statements within them. They are executed concurrently (l.e. to model parallelism such that the order in which statements appear in the model does not matter) with respect to each other whereas the procedural statements are executed sequentially (L.e. the order in which they appear does matter). Both initial and always statements are executed at time-O and then only always statements are executed during the rest of the time. The syntax is as follows: initial [timing controll procedural_statements; always (timing_controll procedural statements; where a procedural_statement is one of: procedural assignment conditional statement case statement loop_statement wait statement The initial statement is non-synthesizable and is normally used in testbenches. The always statement is synthesizable, and the resulting circuit can be a combinatorial or sequential circuit. In order for the model to generate a combinatorial circuit, the always block() should not be edge sensitive. ) every branch of the conditional statement should define all output, and (11) every case of case statement should define all output and must have a default case. More detailed coverage of this topic is covered in Lab 7. The destination (LHS) should be of reg type: either scalar or vector. For example. Teg!! scalar reg lype