BEJ $30503-$ DIGITAL DESIGN

ASSIGNMENT $3$

In this assignment, you are required to design a fully dedicated architecture $($FDA$)$ to

implement the following equation:

$y={\displaystyle \underset{i=1}{\overset{4}{}}}{c}_i{x}_i$

$(1)$ Derive the data flow graph $($DFG$)$ for your design.

$(2)$ Design the corresponding datapath, applying the constrained resource allocation of

one multiplier and one adder.

$(3)$ Write the Verilog code for your datapath and the controller.

$(4)$ Verify your design using ModelSim.

$(5)$ Discuss the results and evaluate your design in terms of resource allocation, execution

time, maximum operating frequency. Assume that the propagation delay if the

multiplier $=100ns,$ adder $=20ns$ and register $=10ns.$

Must do in Quartus prime

Must give in Verilog codes

Show the output waves verified in modelsim

Show the codes in Quartus Prime