Below is a 21x4 register file - it has 2, 4-bit registers. The value of all...

   

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Below is a 21x4 register file - it has 2, 4-bit registers. The value of all inputs overlay the diagram and the current state of the registers overlay the registers (i.e., Q = 0x?). All current input values will remain the same until at least the next positive clock edge. All sets of signals (e.g., wdata [3:0] or D3-D0) order bits from most- to least-significant in hex. Determine the state of the registers immediately after the next positive clock edge. O wdata[3] 1 wdata[2] D3 Q3 D2 Q2 1 wdata[1] 1 wdata[0] D1 Q1 DO clk Q=0xd Q+=0x ? O reset reset enable 0 1 waddr Ao 1 EN 1 w_en D3 Q3 D2 Q2 D1 Q1 DO QO Q=0x1 Q+=0x ? reset enable Below is a 21x4 register file - it has 2, 4-bit registers. The value of all inputs overlay the diagram and the current state of the registers overlay the registers (i.e., Q = 0x?). All current input values will remain the same until at least the next positive clock edge. All sets of signals (e.g., wdata [3:0] or D3-D0) order bits from most- to least-significant in hex. Determine the state of the registers immediately after the next positive clock edge. O wdata[3] 1 wdata[2] D3 Q3 D2 Q2 1 wdata[1] 1 wdata[0] D1 Q1 DO clk Q=0xd Q+=0x ? O reset reset enable 0 1 waddr Ao 1 EN 1 w_en D3 Q3 D2 Q2 D1 Q1 DO QO Q=0x1 Q+=0x ? reset enable