both code for the question and testbench, and screen capture of the wave pls.thks!

1. Write a Verilog/System Verilog module for a N-bit ripple carry adder. N should be parameterized and a module can be means that 1-bit adder should be modeled as a Verilog/System Verilog module. Then write a test bench program to test the module using N-16. Use ModelSim to simulate and test your work (using the waveform panel to confirm the behavior of your adder module). Add a delay to the FAs and observe the delay on the output of the N-bit adder