Question: Build one round AES Encryption and Decryption using VHDL or Verilog and make its full synthesis OR RSA Algorithm encryption and decryption using C/C++ with

Build one round AES Encryption and Decryption using VHDL or Verilog and make its full synthesis OR RSA Algorithm encryption and decryption using C/C++ with text vectors, Python but with no synthesis. Provide the code please.

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