Question: (c) Consider the logic circuit below, suppose that each AND gate has unit time of delay and inverters have negligible delay (a unit time =

(c) Consider the logic circuit below, suppose that each AND gate has unit time of delay and inverters have negligible delay (a unit time = 1step on timing diagram.) Draw the output waveform (2) for the given input values of X & Y. (5 points) X Z time

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