Cache Coherence $(40$ pts$)$

$3.$ Consider the following reference stream:

r$2($A$),$ w$2($B$),$ r$3($A$),$ r$1($A$),$ w$2($B$),$ r$1($B$),$ r$2($A$),$ w$1($B$),$ r$3($A$),$ w$2($A$)$

All of the references in the stream are to the same cache block but for different data words, A

and B within the same cache block. r and w indicate read and write, respectively, and the

digit refers to the processor issuing the reference.

r$1($A$)$

We run MESI protocol. Assume that all caches are initially empty and the accessed cache

block is not evicted while executing the reference stream. Use the following cost model:

$$ Read $/$ write cache hit with no bus access: $1$ cycle

$$ Invalidation broadcasting without requesting the cache block $($BusUpgr$)$: $10$ cycles

$$ Request remote processor to send updated a cache block $($BusRd $/$ BusRdX$)$: $50$ cycles

$$ Request the memory $($or next level cache$)$ to send a cache block $($BusRd$)$: $150$ cycles

Fill the following table with the coherence state of the three processors, coherence message, and

cache hit$/$miss for each memory references. Each column should show the status of the

corresponding data word $($either A or B$).$ Show the total number of cycles used for running the

reference stream