Question: Cache Controller Specification Revision History 1 . 0 1 / 2 5 / 2 0 2 4 Description The Cache controller implements a direct mapped

Cache Controller Specification
Revision History
1.01/25/2024
Description
The Cache controller implements a direct mapped cache supporting a 1MByte memory. The cache is
16Kbytes.
Block Diagram
Requirements:
1. The cache controller shall supports a 1Kbytes chace
2. The cache shall be organized as 256-32 bit words.
3. The cache architecture shall be direct mapped.
4. The cache controller has the following signal

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