Caching in Virtual Memory Systems Assume that you have a system with the following properties and configuration:

- The system is byte-addressable with 16-bit words

- Physical address space: 10 bits; Virtual address space: 16 bits; Page size: 24 bytes

- VIPT L1 D-cache = 48 bytes, 3-way associative, with 8-byte blocks; write-allocate/write-back

- Fully associative 3 entry DTLB; both DTLB and L1 D$ use LRU policy.

- Entry for each TLB or $ entry consists of {valid, dirty, LRU-rank(00=most recent), tag, data}

All metadata is given in binary. TLB data is in binary and $ data is in hexadecimal.

- Endianness: If the data block containing address 0x0006 was 0x0123456789ABCDEF, the word loaded from 0x0006 would have integer value = 0xCDEF.

DTLB: 1,0,00, 0000 1000 0000, 1,0,10, 1101 0000 1101, 1,0,01, 0001 11010000, 00 1100 00 0001 L1 DS: SET 1, 0, 01, 00 1100, 0 0x1234567887654321 OxCD9CEF0990FEDCBA 0xBAD1BAD2BAD3BAD4 1, 0, 00, 00 0001, 0, 0, 10, 01 1001, 1,0, 01, 000001, 1 OxFEEDEEC5DODOFOOD Ox1FEEDEE15DEADCOD 0x0102030405060708 Given the initial contents of the DTLB and L1 D$ as shown, fill in the register value blanks after each instruction executes. Fill in the contents of the DTLB and L1 D$ in the table below, after all instructions below have executed LW $1, Ox1DOC(so) $1-0x LW ADDI $3, $2, 0x1111 $3-0x $2,0 ($1); $2-0x Sw 3,2 (51) DTLB: 1,0,00, 0000 1000 0000, 1,0,10, 1101 0000 1101, 1,0,01, 0001 11010000, 00 1100 00 0001 L1 DS: SET 1, 0, 01, 00 1100, 0 0x1234567887654321 OxCD9CEF0990FEDCBA 0xBAD1BAD2BAD3BAD4 1, 0, 00, 00 0001, 0, 0, 10, 01 1001, 1,0, 01, 000001, 1 OxFEEDEEC5DODOFOOD Ox1FEEDEE15DEADCOD 0x0102030405060708 Given the initial contents of the DTLB and L1 D$ as shown, fill in the register value blanks after each instruction executes. Fill in the contents of the DTLB and L1 D$ in the table below, after all instructions below have executed LW $1, Ox1DOC(so) $1-0x LW ADDI $3, $2, 0x1111 $3-0x $2,0 ($1); $2-0x Sw 3,2 (51)