Question: Calculate the minimum delay in T to compute F= AB + CD using the logic in Figure 1 and Figure 2. Each input can

Calculate the minimum delay in T to compute F= AB + CD using the logic in Figure 1 and Figure 2. Each input can present a maximum of 40% of the transistor width. The output must derive a load equivalent to 2002 of transistor width. Choose transistor sizes to achieve this delay. A B B Figure 1 F A AB CD Figure 2 F

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