Calculator Design - In VHDL

Use maximum length sequence LFSR X^4 + X + 1 to generate pseudorandom sequence at 1 Hz clock rate.

Follow the procedures below.

1. Reset your design using Button 1 (b1).

2. When Button 2 (b2) is logic high, the LFSR is enabled to run, and the values for Q4, Q3, Q2 and Q1 of your LFSR data will be displayed on four LEDs.

3. When Button 2 (b2) is logic low, the LFSR is disabled to run, and the values of Q4, Q3, Q2, Q1 won't change. Connect Q4, Q3, Q2, Q1 with two different 2-bit vectors dout3 and dout4 as following:

dout3 <= Q2 & Q1; dout4 <= Q4 & Q3;

4. Next, perform calculator function according to the values of button b3 and b4.

Table below shows the supported calculator function:

Inputs Outputs Calculator function

b3 b4

0 0 F = dout4 > dout3

0 1 F = dout4 + dout3

1 0 F = dout4 - dout3

1 1 F = dout4 nand dout3

Demo the calculator result F on seven segment display.

At the same time, demo the dout3 and dout4 values on LEDs.