Can someone explain this Verilog-HDL code?

module experiment1A (clk, rst, sw1, ledg);

input clk, rst, sw1 ; output [4:0] ledg;

reg [4:0] state; //state reg [24:0] sw2; //counter reg [24:0] clkcycle; reg counter;

assign ledg = state;

parameter led0 = 4'b0000; parameter led1 = 4'b1000; parameter led2 = 4'b1100; parameter led3 = 4'b1110; parameter led4 = 4'b1111;

always @ (sw1) //this is the part I'm really confused on... is there really a code "clkcycle"? if(sw1 == 0) clkcycle = 2; else clkcycle = 5;

always @ (posedge clk) //counter if (rst == 0) sw2 <= 0; else if (sw2 == clkcycle) sw2 <= 0; else sw2 <= sw2+1; endmodule