Can someone help fix my code? I pasted all my orignal code along with the main objective. It's VHDL code I need this to be able to compile and simulate ModelSim. Thank you!

library IEEE;

use IEEE.STD$\_$LOGIC$\_1164.$ALL;

$--$Define the data type for a $6-$bit word

architecture of word$\_$type is logic$(5$ down o $0)$;

$--$Entity declaration for the memory module

entity memory is

port$($

clock:in std$\_$logic;

Ld :in std$\_$logic;

Memin:in word$\_$type;

writeAddr:in std$\_$logic$\_$vector$(1$ down to $0)$;

readAddr:in std$\_$logic$\_$vector$(1$ down to $0)$;

Memout:out word$\_$type;

$)$;

end entity memory;

$--$Architecture definition for the memory module

architecture Behavioral of memory is

$--$Internal signal declaration

signal register:word$\_$type$\_$array$(0$ to $3)$:$=("000000","000000","000000","000000")$;

begin

$--$Process for loading data based on Ld signal

process$($clock$)$

begin

if rising$\_$edge$($clock$)$ then

if Ld$=\text{'}1\text{'}$ then

register$($to$\_$integer$($writeAddrMemin;

end if;

end if;

end process;

$--$Process for selecting output based on readAddr

process$($clock$)$

if rising$\_$edge$($clock$)$ then

case readAddr is

when $"00"=>$Memoutregister$(0)$;

when $"01"=>$Memoutregister$(1)$;

when $"10"=>$Memoutregister$(2)$;

when $"11"=>$Memoutregister$(3)$;

when others$=>$MemoutXXXXXX$"$;$--$Handle invalid addresses

end case;

end if;

end process;

$--$Tri$-$state buffer for output selection

with tri$\_$state$\_$select is signal $(2$ down to $0)$ is generate

for i in $0$ to $3$ loop

Memout$($iregister$($i$)$ when tri$\_$state$\_$select$($i$)=\text{'}1\text{'}$ else $\text{'}$Z$\text{'}$;

end loop;

end generate;

$--$Connect tri$-$state buffers based on readAddr

tri$\_$state$\_$select when readAddr$="00",$

$"001"$ when readAddr$="01",$

$"010"$ when readAddr$="10",$

$"100"$ when readAddr$="11",$

othefs$=>"000")$;

end architecture Behavioral;