Can someone write a test bench for this d flip flop in verilog

D-flip-flop (DFF) with enable and reset store a single bit

module dff_async_reset (q, data, clk, reset, enable);

input data , clk, reset, enable;

output reg q;

always @ ( posedge clk or negedge reset)

if (~reset) begin

q <= 1'b0;

end

else if (enable) begin

q <= data;

end

endmodule