Can you help me solve the coding problems for this homework. If test bench code is needed I can provide.

$($The remaining parameters, w$\_$fp and w$\_$fp$2,$ are set to the full size of the two

FP formats used, don't change them.$)$ Inputs a and b format

with a w$\_$exp$-$bit exponent and a w$\_$sig$-$bit significand. The total size of each of these inputs is

$1+w_{?}$exp$+$w$\_$sig bits. $($The custom format is recognized by the Chipware modules.$)$ The value on

input c is a w$\_$c$-$bit unsigned integer. The value on output ssum is expected to be a IEEE$-$format

FP number with a w$\_$exp$-$bit exponent and w$\_$sig$2-$bit significand.

The output ssum $($scaled sum$)$ is to be set to $a{2}^s+b$ and output gt is to be set to $1$ if $a{2}^s+b>c$

and $0$ otherwise.

For this problem one should review the IEEE $754$ notes, plus the use of the Verilog concate$-$

nation $($like $\{2^{\text{'}}(b)11,a,4^{\text{'}}d0\}),$ shift and bit slice $(a[6$:$1])$ operators.

$($a$)$ Modify comp$\_$fp so that it computes $a{2}^s$ without using Chipware modules. The value does not

have to be assigned to any particular object, but it should be used to compute $a{2}^s+b.$ To solve

this subproblem one must understand the IEEE $754$ format. A correct solution requires just a line

or two of Verilog code. $($Just one line if overflow is ignored, which is okay.$)$

Compute $a{2}^s$ without Chipware modules.

$($b$)$ Modify comp$\_$fp so that ssum is set to $a{2}^s+b.($For partial credit, or to get started quickly

set ssum to $a+b.$ If this is done correctly the testbench $s=0$ tests should show zero ss errors.$)$

Compute the sum using Chipware modules and the value of $a{2}^s$ from the previous part.

Note that a and b have a w$\_$sig$-$bit significand, but the sum should have a w$\_$sig$2-$bit signif$-$

icand. So$,$ the significands of $a{2}^s$ and $b$ must be lengthened $($assume that w$\_$sig$2>$ w$\_$sig$).$ See

the description of the IEEE $754$ format. Please don't look for a module to do this for you.

Convert $a{2}^s$ and $b$ into FP types with a w$\_$sig$2-$bit significand.

Using the value from the previous part, set ssum to $a{2}^s+b.$

$($c$)$ Modify comp$\_$fp so that gt is correctly set using a floating$-$point comparison. Don't forget that

input c carries an unsigned integer so that to do a FP comparison c will need to be converted.

Set gt$.$

Use Chipware modules for floating$-$point computation and floating$-$point$/$integer conversion.

Use procedural or implicit structural $($assign$)$ code for any integer computation.

Pay attention to cost: don't use more bits than are needed.

The modules must be synthesizable.

Problem $2$: Module comp$\_$int has the same connections as comp$\_$fp and its outputs should be

set to the same values.

$($a$)$ Modify comp$\_$int so that it computes ssum using an instantiation of comp$\_$fp$.$ The ssum output

the comp$\_$fp instance should connect to the ssum output of comp$\_$int. Don't use the gt output

of comp$\_$fp so that the synthesis program doesn't synthesize comp$\_$fp hardware for gt$.$

Compute ssum using an instance of comp$\_$fp a$2^($s$)+$b$>$c where inputs a and $b$ are

real and inputs $s$ and $c$ are non$-$negative integers. Each module has an output gt$,$ which should be

set to $1$ if the comparison is true and $0$ otherwise. There is also an output ssum which should be

set to $a{2}^s+b.$ What makes this interesting is that the sizes of all inputs are parameters, and that

in the instantiations tested the number of bits in the significands of a and $b$ can be less than the

number of bits in $c.$

The floating point calculations and conversion$($s$)$ are to be done using Chipware modules.

Solving this assignment requires a straightforward application of Verilog techniques for instantiating

wirithem tIt also requires an understanding of when and how to convert

two modules are to be completed, comp$\_$fp and coe

greater$-$than comparison is to be done in floating point $($using a Chipware module and in comp$\_$ using an integer c Compute gt using an integer co $//$