Carefully study the following logic circuit and answer the next three questions. ut

If Reset $=0,S_1{S}_0=11,D_3{D}_2{D}_1{D}_0=1011,Q_3{Q}_2{Q}_1{Q}_0=0100,$ at the next positive$-$edge of the clock, then binary output at

$Q_3{Q}_2{Q}_1{Q}_0$ will be Blank $1.$

If Reset $=0,S_1{S}_0=11,D_3{D}_2{D}_1{D}_0=1100,Q_3{Q}_2{Q}_1{Q}_0=0100,$ at the next positive$-$edge of the clock, then binary output at

$Q_3{Q}_2{Q}_1{Q}_0$ will be Blank $2.$

If Reset $=0,S_1{S}_0\frac{?}{b}=ar(00,D_3{D}_2)D_1{D}_0=1011,Q_3{Q}_2{Q}_1{Q}_0=0100,$ at the next positive$-$edge of the clock, then binary output at

$Q_3{Q}_2{Q}_1{Q}_0$ will be Blank $3.$