CDA $3203$ Computer Logic Design Lab $5$:

a$.$ Write VHDL code for each circuit $($USING NAND GATES ONLY$).$

b$.$ Test each design with a testbench for each circuit.

c$.$ Include a timing diagram $($waveform$)$ for each circuit using EPWave.

$4$:$2$ Encoder

$2$:$4$ Decoder

$4$:$1$ Mux

$1$:$4$ Demux