CDA $3203$Computer Logic Design Lab $8$

$1.$Write a VHDL design and testbench for each circuit!!!!!

a$.$Use only logic gates for the circuit architecture!!!

D Flip$-$Flop

JK Flip$-$Flop

T Flip$-$Flop

CDA $3203$ Computer Logic Design Lab $8$

Write a VHDL design and testbench for each circuit.

a$.$ Use only logic gates for the circuit architecture.

Include a timing diagram $($waveform$)$ for each circuit using EPWave.

D Flip$-$Flop

JK Flip$-$Flop

T Flip$-$Flop