Change the module and the testbench of the problem $2$ in a way that you are able to set the internal state of the registers by loading the required PS values to the state registers and being able to read the NS of the registers. $($Problem $2$ refer to the image$).$

a$.[0\mathrm{.}25$ point$]$

Write Verilog code to implement a Finite State Machine $($FSM$)$ represented by the State Transition Table given below. In the State Transition Table, clk is the clock variable, $$ indicates rising edge of the $clk,a$ is an input, PS is the Present State, NS is the Next State and $z$ is the output variable. The machine has a input reset signal that puts the internal states at $S_1.$

$\backslash$table$[[$clk$,PS,a,NS,z$