Change this verilog code to do the addition and subtraction outside of the multiplexer and instead use the multiplexor to decide to show either the addition or subtraction result (1 for addition and 0 for subtraction). Make sure to use different registers for each the addition and subtraction.

Note: A and B are 4 bit inputs. S is the selector. It is to display the result in a 7 segment display.

module AddOrSubtractThenSelectAndDecodeInto7SegmentsDisplay(A,B,S,Result,Overflow,Display);

input [3:0] A; input [3:0] B; input S;

output reg [6:0] Display; output reg [4:0] Result; output reg Overflow;

always @(S or A or B) begin:MUX case (S) 0 : {Result} = A-B; 1 : {Result} = A+B; endcase end

always @(Overflow, Result) begin if(Overflow ==1) begin Result = 4'bx; end else case (Result) 5'b0000: Display = 7'b1111110;//0 5'b0001: Display = 7'b0110000;//1 5'b0010: Display = 7'b1101101;//2 5'b0011: Display = 7'b1111001;//3 5'b0100: Display = 7'b0110011;//4 5'b0101: Display = 7'b1011011;//5 5'b0110: Display = 7'b1011111;//6 5'b0111: Display = 7'b1110000;//7 5'b1000: Display = 7'b1111111;//8 5'b1001: Display = 7'b1111011;//9 5'b1010: Display = 7'b1110111;//A 5'b1011: Display = 7'b0011111;//B 5'b1100: Display = 7'b1001110;//C 5'b1101: Display = 7'b0111101;//D 5'b1110: Display = 7'b1001111;//E 5'b1111: Display = 7'b1000111;//F default: Display = 7'b0011101; endcase end

endmodule