Question: Chapter 5, Problem 9 Computer Organization and Embedded Systems (6th Edition) Consider an instruction set in which instruction encoding is such that register addresses for

Chapter 5, Problem 9

Computer Organization and Embedded Systems (6th Edition)

Consider an instruction set in which instruction encoding is such that register addresses for different instructions are not always in the same bit locations. What effect would that have on the execution steps of the instructions? What would you do to maintain a five-step execution sequence in this case? Assume the same hardware structure as in Figure 5.8.

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