Choose the correct answer.

(a) What is the reason for using a TLB?

1. To reduce page fault time.

2. To reduce the clock cycle time.

3. To reduce address translation time.

4. To speed up cache access

5. Both 1 and 2

(b) The speed of the memory system affects the designers decision on the size of the cache block. Which of the following cache designer guidelines are generally valid? Choose two.

1. The higher the memory bandwidth, the larger the cache block.

2. The higher the memory bandwidth, the smaller the cache block.

3. The shorter the memory latency, the larger the cache block.

4. The shorter the memory latency, the smaller the cache block.

(c) Which of the following combinations of events in the TLB, virtual memory system, and cache is impossible?

1. TLB hit page table miss cache hit

2. TLB hit page table hit cache hit

3. TLB miss page table hit cache hit

4. TLB miss page table hit cache miss

5. TLB miss page table miss cache mi