Choose the most correct answer. Consider the following vectorized program runs on a vector processor

with the following specifications:

No chaining

One memory bank with one port

The memory read and write time is $10$ cycles

The vector multiplier is pipelined with $10$ stages

The execution cannot start before the source vector registers are entirely ready

Then the execution time of this program in the number of clock cycles when it is run on this vector

processor:

MOVI VLEN, $100$ # it will cost one clock cycle

VLD V$1,[$R$1]$ # R$1$ is the base address register

VLD V$2,[$R$2]$ # R$2$ is the base address register

VMUL V$3$V$1$ V$2$

VST V$3,[$R$3]$ # R$3$ is the base address register