cification requires that a NOT-gate be added between register-block output and D t. Propagation delay in the new NOT-gate is 2 ns. Identify if the such a design would (b) A new gate function as expected. Design a clock pulse detector: Consider frequency is F-100 MHz. As in last problem, the clock period will be (t-1/F). If the delay in each of the NOT-gates is 1.5 ns, Draw the timing diagrams of S and CLK PULSE. 7. following clock input connected to NOT gates and AND gates. Assume that the clock Clk CLK PULSE t2 i t2 CLK PUL