class: computer Architecture

My Question is on part b total latency of sw. For part a pipelined is : 300ps slowest stage , part a non pipelined: 900ps sum of all stages, how to solve part b?

The latencies of individual stages in five-stage MIPs Architecture are given below. ID Stage WB IF EX MEM 100ps 100ps Latency 200ps 200ps 300ps a. What is the clock cycle time in a pipelined and non-pipelined processor? Pipelined version Non-pipelined version b. What is the total latency of a sw instruction in a pipelined and non-pipelined processor? Pipelined version Non-pipelined version