Class: Computer Architecture

Objectives At the end of this lab you should be able to: - Investigate Directly Mapped cache organization - Explain what cache hit and miss rates are - Understand one drawback of Directly Mapped cache type - Investigate 2-way Set-Associative cache mapping - Investigate 4-way Set-Associative cache mapping - Explain the effect of cache size and mapping scheme on cache performance Lab Exercises - Investigate and Explore The following exercises require the use of the cache simulator which is part of the CPU-OS Simulator software. The following exercises will use the data cache simulator only. Exercise 1 - Investigating Directly Mapped cache organization Create a new program, call it CacheTest1 and enter the following code: MOV \#0, R01 STBR01,@R01 CMP \#63, R01 JEQ 31 ADD \#1, R01 JMP 6 HLT The above code writes numbers 0 to 63 in memory locations 0 to 63 . Run it and observe the contents of the data in memory. To see the memory click on the SHOW PROGRAM DATA MEMORY... button. Click on the SHOW CACHE... button to display the data cache window. Make sure the Stay on top check box is checked. Now, flush the cache by clicking on the FLUSH button and configure the cache with the following settings: Block Size =4 To execute the above LDB instructions individually, double-click on each of the above LDB instructions. Write down what you observe in the table below: Also make a note of the following data displayed in the Cache Stats frame: Note: % Hits =100% Misses Insert the following LDB instruction after the last LDB instruction above and execute it by double-clicking on it: LDB 4, ROO Write down the additional contents (i.e. in addition to the above data) of the cache below: \begin{tabular}{|l|l|l|} \hline Addr & Data & Block \\ \hline & & \\ \hline & & \\ \hline & & \\ \hline & & \\ \hline \end{tabular} Briefly explain your observations below