Class Worksheet $-$FSM $3$

Design a synchronous binary counter that produces the following count $1,2,3,4,7.$ Answer the following questions

a$)$ Show the state diagram and state table for the counter

b$)$ Implement the counter using T flip$-$flops

c$)$ Implement the counter using JK flip$-$flops

d$)$ Robust design: redesign the counter so that it works even if we start from an unused initial state, i$.$e$.$ states $0,5,6$

e$)$ Write a Behavioral Verilog model for the counter