COD Section $4\mathrm{.}4($A simple implementation scheme$)$ does not discuss I$-$type instructions like ADDI or ANDI

$($a$)$ What additional logic blocks, if any, are needed to add I$-$type instructions to the CPU shown in COD Figure $4\mathrm{.}23($The simple control and datapath...$)?$ Add any necessary logic blocks to COD Figure $4\mathrm{.}23($The simple control and datapath...$)$ and explain their purpose.

$($b$)$ List the values of the signals generated by the control unit for ADDI. Explain the reasoning for any "don't care" control signals. Figure $4\mathrm{.}4\mathrm{.}10$: The simple control and datapath are extended to handle the unconditional branch instruction $($COD Figure $4\mathrm{.}23).$

An additional OR$-$gate $($at the upper right$)$ is used to control the multiplexer that chooses between the branch target and the sequential instruction following this one. One input to the OR$-$gate is the Uncondbranch control signal. Although not shown, the Sign$-$extend logic would recognize the unconditional branch opcode and sign$-$extend the lower $26$ bits of the branch instruction to form a $64-$bit address to be added to the PC$.$