Complete Table $1$ for the expected input and output values for the $16$ bit adder circuit you

are describing in lab $1.$ Note that the syntax used for constant values is from System Verilog

and a$,$ b and f are two$$s complement numbers.

a b f ovf

$16$h$2516$h$45$

$16$hA$41516$hA$555$

$16$hF$11516$hF$215$

$16$h$9$D$0016$h$9$E$00$

$16$hED$0016$hEF$03$

$16$h$8$A$1016$h$7110$

$16$h$21$AA $16$h$21$BB

$16$h$9$A$0016$h$9$F$4$F

Table $1$: Prelab testcases

$2.$ Write a Boolean or System Verilog equation for the overflow output ovf based on input values

a and b$.$ Your equation can also incorporate output f$.$

$3.$ Do the Prelab testcases test every input and output bit? If not which bits are not getting

tested in the given testcases? Write testcases to test these bits