Question: Complete the cycle at which dispatch, issue, writeback and commit happen for the following instruction sequence in a 3 - wide issue processor which can

Complete the cycle at which dispatch, issue, writeback and commit happen for the following
instruction sequence in a 3-wide issue processor which can support one load instruction and multiple
arithmetic/logical instructions in a cycle. The latency of load is 2 cycles and all other operations need 1
cycle. Assume 4 entries in ROB, IQ, LSQ. You have 32 Physical Registers

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