Complete the VERILOG Fibonacci Sequence Generator.

Consult the class notes to complete the controller for the Fibonacci Sequence Generator. The test bench will check for the sequence: 1, 1, 2, 3, 5, 8.

An incomplete version of the controller is:

module controller( output as_ctl_t as_ctl, output shift_ctl_t shift_ctl, output logic r1_ld, r0_ld, output logic ready, input logic next, input clk, reset ); logic [2:0] step; task ctrl(logic rdy, as_ctl_t as, shift_ctl_t sh, logic r1, logic r0); begin ready <= rdy; as_ctl <= as; shift_ctl <= sh; r1_ld <= r1; r0_ld <= r0; end endtask always_ff @(posedge clk) begin if ( reset ) begin step <= 0; ctrl(0, AS_A, SH_PASS, 0, 0); end else begin case( step ) 0: begin step <= next ? 1 : 0; ctrl(0, AS_A, SH_PASS, 0, 0); end // complete the reset endcase end end endmodule