Complex FSM Design $($run detector$)$

For this assignment you will design a FSM that will control several registers to count

runs of length $4$ or greater of a $4-$bit input that exceed a threshold.

All the supporting

blocks are already

implemented in verilog.

Your responsibility is to

implement and validate

the FSM block.

When strtCapCmp is

asserted the machine

will capture the current

value of sig in reg$4.$

This will be used as a

threshold for comparing subsequent values of sig. If the value of sig exceeds the

captured value $($held in reg$4)$ for $4$ or more consecutive clock cycles the counter that

forms N$\_$abv $($cnt$4)$ will be incremented. cht$2$ is a $2-$bit free running counter that can

be synchronously reset. Its TC $($terminal count$)$ output is true when the count is $2\text{'}$b$11.$

mag$4$ is a simple unsigned magnitude comparator that asserts gt when sig$>$thres.

Once a run of numbers causes an increment of N$\_$abv, it cannot be incremented again

until a value of sig is less than or equal to the captured reference value. Please draw out the FSM